Feb 23, 2007
ARMO Meeting Minutes
Elliot
- got testbench working for H.264
- learning curve with Chun-Chieh's code
Daniel
- inter block working in Verilog
- hoping to make it synthesizable in 2 weeks
- deblocking might be ready in 2 weeks
Jae
- working on FPGA
- scheduling the transactors
- using multiple FPGA's for simulation
Murali
- working on decoder channel estimator
Alfred
- completed FFT
- implementation is combination of partial/circ/pipeline
- similar structure might also work for viterbi
NrcArch/2007-02-23 (last edited 2007-03-29 20:31:33 by JameyHicks)
